1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having a low-k dielectric layer.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, techniques employing multi-layered metal interconnections for forming these devices have also become more widely used. In particular, the multi-layered metal interconnections should be formed of metal layers which have low resistivity and high reliability for enhancing the performance of the semiconductor device. Moreover, an insulating layer located between the multi-layered metal interconnection should be formed of a low-k dielectric layer. For example, a copper (Cu) layer is widely used as the metal layer. However, it is difficult to pattern a Cu layer using typical photolithography and etching processes. Accordingly, a damascene process is widely used to pattern the metal layer, e.g. a Cu layer.
An insulating layer with a dielectric constant of less than 2.5 is used for the low-k dielectric layer. Examples of the above described insulating layer include silicon oxycarbide (SiOC) layer, a carbon-doped silicon oxide (SiOCH) layer, or a silicon oxyfluoride (SiOF) layer. The low-k dielectric layer should also have a porous sponge structure, so that absorption is apt to occur.
FIGS. 1A to 1G are cross-sectional views illustrating a conventional method of fabricating a semiconductor device having a low-k dielectric layer.
Referring to FIG. 1A, a lower insulating layer 10 is formed on a semiconductor substrate 5. A lower interconnection 12 is then formed within the lower insulating layer 10 using a typical damascene technique. The lower interconnection 12 may be formed of a copper layer or a tungsten layer.
Next, in the above conventional method, an etch stop layer 15 and a low-k dielectric layer 17 are sequentially formed on the semiconductor substrate 5 having the lower interconnection 12. The etch stop layer 15 is formed of a silicon nitride layer. The low-k dielectric layer 17 is formed of a single low-k dielectric layer for enhancing the operating speed of the semiconductor device and also to prevent an interface from being formed within the low-k dielectric layer 17. The single low-k dielectric layer may be formed of a silicon oxide layer containing carbon (C), fluorine (F), or hydrogen (H). For example, a silicon oxycarbide (SiOC) layer, a carbon-doped silicon oxide (SiOCH) layer, or a silicon oxyfluoride (SiOF) layer are all materials which may be used in forming the low-k dielectric layer 17. In addition, the low-k dielectric layer 17 has a porous sponge structure and may be degraded due to damage in subsequent processes. Accordingly, a capping layer 20 for protecting the characteristics of the low-k dielectric layer 17 is formed on the low-k dielectric layer 17. The capping layer 20 may be formed of a tetra ethyl ortho silicate (TEOS) layer or an undoped silicate glass (USG) layer. A mask layer is formed on the capping layer 20 and patterned to form a mask pattern 23. The mask pattern 23 may be formed of a photoresist layer or a hard mask layer.
Referring to FIG. 1B, the capping layer 20 and the low-k dielectric layer 17 are sequentially dry etched using the mask pattern 23 as an etch mask, thereby forming a preliminary via hole 25 which exposes the etch stop layer 15 above the lower interconnection 12. At the time of the dry etching, a gas containing fluorine atoms, for example, CxFy or CHxFy is used as the etch gas. Moreover, as mentioned, the low-k dielectric layer 17 has a porous sponge structure, so that fluorine atoms (F) are absorbed into the low-k dielectric layer 17 when the low-k dielectric layer 17 is dry etched using the gas containing the fluorine atoms.
Referring to FIG. 1C, a sacrificial layer 30 is formed which buries the preliminary via hole 25 on the semiconductor substrate having the preliminary via hole 25. A photoresist pattern 32 is then formed on the sacrificial layer 30. The sacrificial layer 30 is formed of a layer having a wet etch selectivity with respect to the low-k dielectric layer 17. The sacrificial layer 30 is formed to prevent deformation of the profile of the preliminary via hole 25 in subsequent processes. The sacrificial layer 30 may be formed of a hydro-silsesquioxane (HSQ) layer or organic siloxane. Moreover, hydrogen or moisture (H2O) is absorbed into the low-k dielectric layer 17 while the sacrificial layer 30 is being formed. The above absorption of hydrogen or moisture causes the formation of hydrofluoric acid (HF) in the low-k dielectric layer 17, due to a reaction between the hydrogen or moisture with the fluorine atoms (F) which were already absorbed into the low-k dielectric layer 17 at the time of the dry etching. Consequently, the silicon oxide layer based low-k dielectric layer 17 is internally dissolved by the above generated fluoric acid (HF), thereby causing voids (A) to form in the low-k dielectric layer 17.
Referring to FIG. 1D, the sacrificial layer 30, the mask pattern 23, the capping layer 20, and the low-k dielectric layer 17 are then sequentially dry etched using the photoresist pattern 32 as an etch mask, thereby forming a trench region 35 which crosses over the preliminary via hole 25 and which is positioned within the low-k dielectric layer 17. In this case, a sacrificial layer 30a remains within the preliminary via hole 25. A gas containing fluorine atoms, for example, CxFy or CHxFy, is used as the etch gas at the time of the dry etching. Accordingly, as described with reference to FIG. 1B, the low-k dielectric layer 17 has a porous sponge structure, so that the fluorine atoms (F) are absorbed into the low-k dielectric layer 17 through a sidewall of the trench region 35 when it is dry etched using the gas containing the fluorine atoms.
Referring to FIG. 1E, the sacrificial layer 30a within the preliminary via hole 25 and the sacrificial layer 30 above the low-k dielectric layer 17 are removed, thereby exposing the etch stop layer 15 on the bottom surface of the preliminary via hole 25. The sacrificial layers 30 and 30a are removed using a wet solution. Moreover, the sacrificial layer 30a has a wet etch selectivity with respect to the low-k dielectric layer 17, so that a surface of the low-k dielectric layer 17 is prevented from being damaged due to etching.
The etch stop layer 15 exposed on the bottom surface of the preliminary via hole 25 is then removed to form a final via hole 25a which exposes the lower interconnection 12. The etch stop layer 15 is removed using a dry etching process. A portion of the mask pattern 23 may be etched while the etch stop layer 15 is etched. Hydrogen or moisture (H2O) is absorbed into the low-k dielectric layer 17 to react with the fluorine atoms (F) which have already been absorbed at the time of the dry etching process, so that fluoric acid (HF) is also formed as described with reference to FIG. 1C in the process of removing the sacrificial layers 30 and 30a and the process of forming the final via hole 25a. Accordingly, the low-k dielectric layer 17 is internally dissolved by the above generated fluoric acid (HF), so that voids A occur within the low-k dielectric layer. In addition, in the event that voids have already been formed in the low-k dielectric layer 17, the above dissolving reaction may proceed to cause further enlargement of these voids A1 to occur.
Referring to FIG. 1F, an upper metal layer is formed on the semiconductor substrate having the final via hole 25a. The upper metal layer may be formed by sequentially stacking a barrier metal layer 40 and a metal layer 45. The barrier metal layer 40 may be formed of tantalum nitride (TaN) or titanium nitride (TiN), and the metal layer 45 may be formed of copper. The metal layer 45 is formed in a manner such that a Cu seed layer 42 is formed on the barrier metal layer 40 by a sputtering method and then a plating method is carried out thereon using the Cu seed layer 42. After the metal layer 45 is formed, heat treatment is carried out for enhancing the electrical characteristics of the metal layer 45. However, heat treatment may cause the above-mentioned dissolving reaction in the low-k dielectric layer 17 due to the hydrofluoric acid (HF) to proceed even further, thereby causing even larger voids A2 to be formed in the low-k dielectric layer 17.
Referring to FIG. 1G, the metal layer 45, the Cu seed layer 42, and the barrier metal layer 40 are planarized to form an upper interconnection which fills the trench region 35 and the final via hole 25a. The mask pattern 23 may be removed at the same time in the planarization process. The upper interconnection is composed of a barrier metal layer 40a, a Cu seed layer 42a, and a metal layer 45a which are planarized. The planarization process may be carried out using a chemical mechanical polishing process. It is noted, however, that, the shape of the low-k dielectric layer 17 may be deformed by the voids A2 during the chemical mechanical polishing process. Consequently, a short circuit may occur in an undesired region between metal interconnections, and thus subsequent processes may encounter difficulties due to the above-mentioned deformation.
Accordingly, there is a need for a method for preventing voids from forming within a low-k dielectric layer, during the dry-etching stage or stages of fabricating this layer.